Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves
Identifieur interne : 002465 ( Main/Exploration ); précédent : 002464; suivant : 002466Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves
Auteurs : Jean-Luc Beuchat [Japon] ; Jérémie Detrey [France] ; Nicolas Estibals [France] ; Eiji Okamoto [Japon] ; Francisco Rodríguez-Henríquez [Mexique]Source :
- IEEE Transactions on Computers [ 0018-9340 ] ; 2011-02-01.
Abstract
This paper is devoted to the design of fast parallel accelerators for the cryptographic $\eta_T$ pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the $\eta_T$ pairing over $\F_{2^m}$ and $\F_{3^m}$. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the $\eta_T$ pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previously published coprocessors.
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DOI: 10.1109/TC.2010.163
Affiliations:
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type="acronym">LCIS</orgName><desc><address><addrLine>1-1-1 Tennodai, Tsukuba, Ibaraki, 305-8573</addrLine><country key="JP"></country></address></desc><listRelation><relation active="#struct-366135" type="direct"></relation></listRelation><tutelles><tutelle active="#struct-366135" type="direct"><org type="institution" xml:id="struct-366135" status="VALID"><orgName>University of Tsukuba</orgName><desc><address><addrLine>1-1-1 Tennodai, Tsukuba, Ibaraki 305-8577 Japan</addrLine><country key="JP"></country></address><ref type="url">http://www.tsukuba.ac.jp/english/</ref></desc></org></tutelle></tutelles></hal:affiliation><country>Japon</country></affiliation></author><author><name sortKey="Rodriguez Henriquez, Francisco" sort="Rodriguez Henriquez, Francisco" uniqKey="Rodriguez Henriquez F" first="Francisco" last="Rodríguez-Henríquez">Francisco Rodríguez-Henríquez</name><affiliation wicri:level="1"><hal:affiliation type="institution" xml:id="struct-89939" status="VALID"><orgName>Centro de Investigacion y de Estudios Avanzados del Instituto Politécnico Nacional</orgName><orgName type="acronym">CINVESTAV</orgName><desc><address><addrLine>Avenida Politécnico Nacional 2508 Mexico-D.F. 07360</addrLine><country key="MX"></country></address><ref type="url">http://www.cinvestav.mx/</ref></desc></hal:affiliation><country>Mexique</country></affiliation></author></analytic><idno type="DOI">10.1109/TC.2010.163</idno><series><title level="j">IEEE Transactions on Computers</title><idno type="ISSN">0018-9340</idno><imprint><date type="datePub">2011-02-01</date></imprint></series></biblStruct></sourceDesc></fileDesc><profileDesc><textClass></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">This paper is devoted to the design of fast parallel accelerators for the cryptographic $\eta_T$ pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the $\eta_T$ pairing over $\F_{2^m}$ and $\F_{3^m}$. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the $\eta_T$ pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previously published coprocessors.</div></front></TEI><affiliations><list><country><li>France</li><li>Japon</li><li>Mexique</li></country><region><li>Grand Est</li><li>Lorraine (région)</li></region><settlement><li>Metz</li><li>Nancy</li></settlement><orgName><li>Université de Lorraine</li></orgName></list><tree><country name="Japon"><noRegion><name sortKey="Beuchat, Jean Luc" sort="Beuchat, Jean Luc" uniqKey="Beuchat J" first="Jean-Luc" last="Beuchat">Jean-Luc Beuchat</name></noRegion><name sortKey="Okamoto, Eiji" sort="Okamoto, Eiji" uniqKey="Okamoto E" first="Eiji" last="Okamoto">Eiji Okamoto</name></country><country name="France"><region name="Grand Est"><name sortKey="Detrey, Jeremie" sort="Detrey, Jeremie" uniqKey="Detrey J" first="Jérémie" last="Detrey">Jérémie Detrey</name></region><name sortKey="Estibals, Nicolas" sort="Estibals, Nicolas" uniqKey="Estibals N" first="Nicolas" last="Estibals">Nicolas Estibals</name></country><country name="Mexique"><noRegion><name sortKey="Rodriguez Henriquez, Francisco" sort="Rodriguez Henriquez, Francisco" uniqKey="Rodriguez Henriquez F" first="Francisco" last="Rodríguez-Henríquez">Francisco Rodríguez-Henríquez</name></noRegion></country></tree></affiliations></record>Pour manipuler ce document sous Unix (Dilib)
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